June 9, 2025 10:00 PST | Source: Baum Design Systems Co., Ltd.

SEOUL, South Korea – June 9, 2025 – Baum Design Systems, a provider of innovative electronic design automation (EDA) tools for power analysis and verification, announced new product enhancements that accelerate early-stage, silicon-correlated power insights for chip designers. The company will showcase these updates at Booth #1711 during the 2025 Design Automation Conference (DAC), held from June 22 to 25 at Moscone West, San Francisco, CA, USA. 

“As chip designs become increasingly complex and power efficiency remains a top priority, designers need tools that deliver accurate, actionable power insights earlier in the development cycle,” said Seungwhun Paik, CEO of Baum Design Systems. “Our latest innovations across PowerSpion, PowerWurzel, PowerBaum, and PowerMesser directly address these critical needs, enabling our customers to optimize power with unprecedented speed and confidence, from RTL to silicon.” 

Baum’s latest innovations include: 

The PowerSpion: Intuitive RTL Clock Gating Analysis 

PowerSpion is Baum’s lightweight RTL-level tool for clock gating analysis and efficiency profiling. It delivers key metrics like CGR (clock gating ratio), CGE (clock gating efficiency), ICGE (ideal clock gating efficiency), ACR (active clock ratio), and IACR (ideal active clock) waveform without the need for power estimation or synthesis, making it ideal for fast, iterative RTL development. 

PowerSpion now comes with an intuitive graphical user interface (GUI), allowing users to easily navigate modules or time windows with low clock gating metrics or power-proxy waveforms. ACR and IACR waveform visualization further helps designers understand power trends under specific scenarios, enabling informed low-power design decisions. 

The PowerWurzel: Advanced Gate-Level Power Analysis with RTL-to-Gate-level Activity Conversion 

PowerWurzel is Baum’s gate-level power analysis solution. It can be integrated with PowerBaum (while the power model is generated) or used as a stand-alone product. It accepts RTL simulation vectors and internally converts them to gate-level vectors (e.g. FSDB, VCD), eliminating the need for expensive gate-level simulation runs.  

We also introduced a gate-level timing validation feature built on top of RTL-to-gate-level power analysis engine. By detecting timing violations early, users can catch potential issues in timing constraints and ease the burden of late-stage timing closure. This enhancement pushes timing verification further left in the design cycle, delivering accurate insights without the runtime overhead and complexity of traditional gate-level simulations. 

The PowerBaum: Full-Chip Power Profiling of Real Software Workload 

PowerBaum enables fast and accurate full-chip power analysis by generating compact power models that run seamlessly within RTL simulation or emulation environments. 

PowerBaum automatically identifies and uses only the key signals that correlate strongly with real power behavior, significantly reducing modeling overhead while maintaining high accuracy. PowerBaum delivers 50x to 100x faster performance than gate-level power analysis, which is too slow for analyzing real software workload. 

The PowerMesser: Real-Time On-Chip Power Monitoring 

PowerMesser is a lightweight on-chip power meter that enables real-time power monitoring of your silicon. It delivers fine-grained, cycle-level visibility into power behavior, making it ideal for DVFS control, thermal management, and detailed silicon power debugging. By embedding power observability directly into silicon, PowerMesser bridges the gap between software-based estimates and actual silicon behavior—empowering more efficient and responsive power management. 

About Baum

Baum provides innovative electronic design automation (EDA) tools and solutions for advanced power analysis and optimization of semiconductor designs. Our technology enables customers to maximize energy efficiency from the early stages of the design cycle, accelerating development while reducing cost and risk. Founded in 2013 by experienced semiconductor professionals with deep expertise in engineering, R&D, and business development, Baum is a privately held and self-funded company committed to empowering power-aware design through practical, scalable EDA innovation. 

Connect with Baum at:

Website: www.baum-ds.com
Email: contacts@baum-ds.com
LinkedIn: https://www.linkedin.com/company/baum-ds

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For more information, contact:
DongChul (DC) Chung
Baum, Inc CBO
(82) 10-5358-9958
contacts@baum-ds.com