PowerSpion Features
How PowerSpion Works
PowerSpion automatically extracts clock gating structure from RTL design and reports clock-gating metrics (e.g. CGR, CGE, CGEE, OCGR) without running computation-expensive power estimation.
Once dump files (FSDB or VCD) are prepared (flow 1), user can run PowerSpion to generate clock-gating metrics based on both instantiated and inferred ICGs from RTL design.
If dump files are not available (flow 2), user can build OCGR model upfront and use the model later to analyze clock-gating metrics once simulation environment become accessible.
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flow 1: Stand-alone flow
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flow 2: Build OCGR model
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flow 2: Run OCGR model with simulator to generate reports
Operational Clock Gating Ratio (OCGR)
OCGR is defined as the percentage of flip-flops whose gated clock remains inactive during each clock cycle.
The figure illustrates that the inverted OCGR (i.e. OCGR is subtracted from 1.0) shows strong correlation with the gate-level power profile. This metric proves valuable in guiding power-aware RTL development, particularly in scenarios where dynamic power constitutes a significant portion of the total power, such as in advanced technology nodes and data-intensive applications.
Clock Gating Linting
PowerSpion conducts thorough checks on RTL designs, detecting any erroneous usage of clock gating without requiring vectors. Following are some of the cases we support.
- Constant ICG
- Floating ICG
- Redundant cascaded ICG
- Memory w/o ICG
RTL CI/CD Pipeline
Users can facilitate power-aware RTL development by seamlessly integrating PowerSpion into RTL CI/CD pipeline.
RTL engineers can track the progress of clock-gating metrics throughout the development cycle to strengthen their confidence in power quality of their design.
Team lead leverage this data to drive power-aware RTL sign-off.
PowerSpion Demo
TBD