PowerSpion Features
- Super fast and lightweight tailored for RTL CI/CD
- Automatically extract ICGs from RTL structure and compute various clock gating metrics (CGR, CGE, ICGE)
- Clock gating linting
- 100x faster power analysis using Power-proxy Calibrated Model (PCM)
How PowerSpion Works
PowerSpion automatically extracts clock gating structure from RTL design and reports clock-gating metrics (e.g. CGR, CGE, ICGE) without running computation-expensive power estimation.
Once RTL vectors (e.g. VCD) are prepared, user can run PowerSpion to generate clock-gating metrics based on both instantiated and inferred ICGs from RTL design to generate clock-gating metrics reports as well as power-proxy waveforms.
If RTL vectors are not available in the early stage, users can perform vectorless clock-gating analysis to estimate CGE until a testbench becomes available.
Infer ICGs from RTL design
Super fast clock-gating analysis
Vectorless clock-gating analysis
Power-proxy Calibrated Model
Calibrate power proxies using just a few signoff power samples to enable fast, scalable, and accurate power profiling across diverse workloads—delivering up to 100× faster analysis than conventional gate-level methods.
Clock Gating Linting
PowerSpion conducts thorough checks on RTL designs, detecting any erroneous usage of clock gating without requiring vectors. Following are some of the cases we support.
- Constant ICG
- Floating ICG
- Redundant cascaded ICG
- Memory w/o ICG
RTL CI/CD Pipeline
Users can facilitate power-aware RTL development by seamlessly integrating PowerSpion into RTL CI/CD pipeline.
RTL engineers can track the progress of clock-gating metrics throughout the development cycle to strengthen their confidence in power quality of their design.
Team lead leverage this data to drive power-aware RTL sign-off.
