Jun 16, 2023: Baum Design Systems Showcases End-to-End SoC Power Ananlysis Solutions
Baum Design Systems today launched the latest version of its SoC power analysis solutions PowerWurzel, Power Spion, and PowerBaum. Baum will showcase the products in Booth #1550 at the Design Automation Conference (DAC), held from Jul 10th to 14th at the Moscone Convention Center, San Francisco, CA, USA.
2022.12.22: 반도체 전력분석 솔루션 바움, 50억 시리즈A 투자 유치
반도체 전력분석 EDA(Electronic Design Automation) 솔루션 기업 ‘바움디자인시스템즈(이하 바움)’가 50억원의 시리즈A 투자 유치에 성공했다. 최근 VC업계 전반의 투자 심리가 위축된 상황에서도, LB인베스트먼트는 글로벌 기술 경쟁력을 갖고 있는 바움의 기술력을 높이 평가해 단독 FI로 베팅한 것으로 보인다.
October 19, 2022: Baum’s Power Analysis Suite is Adopted for ASICLAND SoC Design Flow
Baum, electronic design automation (EDA) company, announced today that its flagship product, PowerBaum, is adopted for ASICLAND SoC design flow. ASICLAND is a company that provides design services as its main business; with PowerBaum in its SOC design support flow, the company now provides power analysis services to customers in the early stages of design.
July 11, 2022: Baum’s Power Analysis Suite is Adopted by SiliconArts
Baum today announced that SiliconArts, a fabless semiconductor company focusing on ray-tracing GPU architecture, used Baum’s power analysis suite to lower both peak power and average power consumption of their GPU, RAIV, and plan to continue applying it in the design of next-generation chips.
2021.12.12: [시스템반도체 유니콘]바움, 빠른 반도체 전력 분석 솔루션 개발
바움(이준환·신영수)은 각종 디바이스에 들어가는 반도체 전력소모를 효율적으로 분석해 절감하는 솔루션 ‘파워바움’ 개발했다. 파워바움은 핵심 전력 신호를 추출하고, 자체 분석 툴에 적용해 작동하는 방식이다.
Nov 22, 2021: Baum Showcases Power Modeling for AI Chips
Baum will showcase the latest PowerBaum in Booth #2430 at the Design Automation Conference (DAC), held from Dec 5th to 9th at the Moscone Convention Center, San Francisco, CA, USA.
Nov 22, 2021: Baum’s Power Analysis Suite is Adopted by FuriosaAI
Baum today announced that FuriosaAI used Baum’s power analysis suite to lower both peak power and average power consumption of their AI chip, Warboy, and plan to continue applying it in the design of next generation chips.
