Baum Showcases Innovative EDA Solutions to Shift-Left and Accelerate Sustainable Silicon

June 10, 2024 10:00 PST | Source: Baum Design Systems Co., Ltd.

Seoul, South Korea, June 10, 2024 – Baum Design Systems offers innovative electronic design automation (EDA) products and solutions for analyzing power of chip designs enabling our customers to fully optimize the energy efficiency of their designs in early stage of design cycle. Baum will be attending DAC 2024 and will share the updated advantages of its products and solutions in Booth #1331 at the Design Automation Conference (DAC), held from June 24th to 26th at the Moscone West, San Francisco, CA, USA.

The PowerSpion

One of Baum’s flagship offerings, PowerSpion, provides comprehensive clock gating linting and efficiency analysis based on extracted clock gating structures from RTL designs. PowerSpion focuses on delivering essential clock gating efficiency metrics, such as CGR (clock gating ratio), CGE (clock gating efficiency), CGEE (clock gating enable efficiency), and OCGR (operational clock gating ratio). PowerSpion provides accurate clock gating metrics without the need for computation-intensive power estimation, which often suffers from large errors and slow runtime, making it faster and more lightweight than other tools. The OCGR waveform is particularly useful for customers who need to monitor scenario-specific power waveform as it aligns closely with cycle-accurate power profiles.

In addition to clock gating efficiency metrics, PowerSpion offers a range of clock gating linting capabilities to identify and report erroneous usage of clock gating in designs without requiring vector-based analysis. These features empower RTL developers to seamlessly integrate low-power design considerations into their daily workflows without the overhead of time-consuming gate-level power analysis.

The PowerBaum

PowerBaum automatically generates power models from design sources and characterizes gate-level behavior to achieve very high accuracy. The power models run in higher abstraction environments, such as RTL/ESL simulation and hardware emulation to achieve orders of magnitude performance improvement compared to competing solutions in the market. PowerBaum facilitates system-level simulations with realistic workloads, enabling users to generate power profiles spanning billions of clock cycles. These profiles can then be analyzed for power debugging purposes. With dynamic power analysis capabilities, users can easily pinpoint the specific parts of the design consuming excessive power and take corrective action.

The latest version supports a new feature of “Power Equation”, which is a much simplified power model. The equation can be tailored for HW power monitor implementation, facilitating real-time and fine-grained power management decisions such as Dynamic Voltage and Frequency Scaling (DVFS) to meet power and thermal budget or alleviate voltage drops.

The PowerWurzel

PowerWurzel is Baum’s gate-level power analysis solution. It can be integrated with PowerBaum (while power model is generated), or can be used as a stand-alone product. It can read in RTL FSDB as well as standard gate-level FSDB; the conversion of RTL to gate-level FSDB is performed internally before actual power analysis is performed on the netlist. The conversion itself can be used as a useful function because extraction of gate-level FSDB through simulation is an expensive process.

 

One of Korea’s largest fabless AI accelerator companies recently adopted PowerSpion and plan to use it for optimizing power consumption of its flagship AI chip. Additionally, the country’s leading enterprise SSD controller company adopted PowerSpion to drive power-aware RTL development.

About Baum

Baum provides innovative electronic design automation (EDA) products and solutions for analyzing power of chip designs enabling our customers to fully optimize the energy efficiency of their designs in early stage of design cycle. Founded in 2016 by seasoned semiconductor professionals with technical, R&D, and business development expertise, Baum is privately held and funded.

Connect with Baum at:

Website: www.baum-ds.com
Email: contacts@baum-ds.com
LinkedIn: https://www.linkedin.com/company/baum-ds

All trademarks and registered trademarks are the property of their respective owners.

For more information, contact:
DongChul (DC) Chung
Baum, Inc CBO
(82) 10-5358-9958
contacts@baum-ds.com

Baum proudly sponsors ASP-DAC 2024

Baum Design Systems is pleased to announce that it will be sponsoring the 2024 Asia South Pacific Design Automation Conference (ASP-DAC 2024), which will be held in Incheon Songdo, South Korea on January 22-25, 2024. Baum will be participating as a Silver Sponsor.

About Baum

Baum provides innovative electronic design automation (EDA) products and solutions for analyzing power of chip designs enabling our customers to fully optimize the energy efficiency of their designs in early stage of design cycle. Founded in 2016 by seasoned semiconductor professionals with technical, R&D, and business development expertise, Baum is privately held and funded.

Connect with Baum at:

Website: www.baum-ds.com
Email: contacts@baum-ds.com
LinkedIn: https://www.linkedin.com/company/baum-ds

All trademarks and registered trademarks are the property of their respective owners.

Baum Design Systems showcases End-to-End SoC power analysis solutions

Will showcase PowerWurzel, Power Spion, and PowerBaum at DAC Jul 10-14 at the Moscone Convention Center, San Francisco, CA, USA

Jun 16, 2023 11:00 ET | Source: Baum Design Systems Co., Ltd.

Seoul, South Korea, Jun. 16, 2023 – Baum Design Systems today launched the latest version of its SoC power analysis solutions PowerWurzel, Power Spion, and PowerBaum. Baum will showcase the products in Booth #1550 at the Design Automation Conference (DAC), held from Jul 10th to 14th at the Moscone Convention Center, San Francisco, CA, USA.

The Latest Version of PowerBaum

PowerBaum automatically generates power models from design sources and characterizes gate-level behavior to achieve very high accuracy. The power models run in higher abstraction environments, such as RTL/ESL simulation and hardware emulation to achieve orders of magnitude performance improvement compared to competing solutions in the market.
The new release supports power analysis with FSDB files generated in a hardware emulation. “Baum power models can accurately analyze power consumption considering glitches with emulator-generated FSDB files,” said Joonhwan Yi and Youngsoo Shin, Baum’s CEO. “Combining implementation-accurate Baum power models with hardware emulation creates an ideal solution for identifying and analyzing power problems under real operating conditions of large systems.” Users have seen over 1,000 times speed-up compared to competing power analysis solutions when PowerBaum is used together with hardware emulation.
The latest version supports a new feature of “Power Equation”, which is a much simplified power model. The equation can be tailored for HW power monitor implementation.

The Introduction of PowerSpion

Baum debuts a new product named PowerSpion. It reads in RTL Verilog source together with FSDB, and reports clock gating efficiency and offers power optimization guidelines. Clock gating efficiency includes CGE (clock gating efficiency), the percentage of cycles when each flop or register is gated; OCGR (operational clock gating ratio), the percentage of flops that are gated cycle by cyles (in a waveform); CGEE (clock gating enable efficiency), the percentage of cycles when each flop is actually gated over the ideal cycles when flop can be gated; and CGR (clock gating ratio), the percentage of flops that are controlled by ICG (integrated clock gating) cells. These reports are very useful while RTL is designed or debugged with clock gating implementation.
PowerSpion also offers a few power optimization guidelines. These include detection of RTL power inefficiency, e.g. constant clock gating enable signals, cascaded ICGs driven by the same enable signals, floating clock, memory macros without clock gating, etc.

The PowerWurzel

PowerWurzel is Baum’s gate-level power analysis solution. It can be integrated with PowerBaum (while power model is generated), or can be used as a stand-alone product. It can read in RTL FSDB as well as standard gate-level FSDB; the conversion of RTL to gate-level FSDB is performed internally before actual power analysis is performed on the netlist. The conversion itself can be used as a useful function because extraction of gate-level FSDB through simulation is an expensive process.
The latest PowerWurzel supports clock mesh as well as standard clock tree; power analysis at multiple voltage-temperature corners is another unique feature.
Furiosa AI, a fabless semiconductor company, used Baum’s power analysis suite to lower both peak power and average power consumption of their AI chip, Warboy, and plans to continue applying it in the designs of next generation chips. Recently, LXSemicon, one of the largest global display IC companies, adopted PowerBaum in developing their digital driver ICs (DDIs). ASICLAND, the only TSMC VCA in Korea, includes PowerBaum in the design process to provide RTL level power analysis service of customer design.

 

About Baum

Baum provides electronic design automation (EDA) software and solutions that enable engineering groups in the mobile, artificial intelligence/machine learning, automotive, internet of things (IoT), networking and server markets to fully optimize the energy efficiency of their semiconductor designs. Founded in 2016 by seasoned semiconductor professionals with technical, R&D, and business development expertise, Baum is privately held and funded.

Connect with Baum at:

Website: www.baum-ds.com
Email: contacts@baum-ds.com
LinkedIn: https://www.linkedin.com/company/baum-ds

All trademarks and registered trademarks are the property of their respective owners.

For more information, contact:
DongChul(DC) Chung
Baum, Inc CBO
(82) 10-5358-9958
contacts@baum-ds.com