Overview
Baum’s products were conceived to solve real world power issues in today’s demanding designs. They fill a large gap in the solution space by providing breakthrough speed and accuracy never seen before in combination. Now, with Baum’s innovative products, designers and architects can analyze and optimize power and thermal dissipation on their chip designs using real world workloads. These capabilities provide users with confidence that their designs will meet the power and thermal budgets prior to tape-out. Our customers have used Baum’s products to lower both the average, transient, and peak power consumption in their designs. Baum’s products expose power issues and guide users to their solutions.
“Having a solution that achieves both the speed necessary to run a variety of realistic scenarios, combined with providing a very high level of accuracy, allowed us to uncover power problems quickly and identify where to make the fixes. Without Baum’s unique power analysis capabilities, we wouldn’t have been able to find and fix these issues causing our new product to consume too much power,” remarks Moon-Soo Kim, vice president of engineering at Telechips.
PowerBaum
PowerBaum is our patented and award-winning flagship product which automatically creates an extremely fast, accurate, and portable power model. PowerBaum represents a breakthrough in power analysis technology combining orders of magnitude speed-up in power analysis performance while maintaining near gate-level power analysis accuracy. This combination of speed and accuracy is unique in the industry and allows the designers to understand and solve real world power, thermal, and other power related problems. (See our solutions page for more information on how PowerBaum can help solve your problems.)
PowerBaum reads in a design’s source description (RTL and its gate-level netlist) and automatically generates a high-performance power model. PowerBaum relies on a few sample gate-level power simulations (PowerWurzel) to build and train the model with gate-level accuracy. Once the power model is trained, it can be used in many simulation environments executing large workloads with a high level of accuracy.
PowerBaum models can be integrated into RTL simulations (VCS, Incisive, Model Tech, etc.), ESL/Virtual Platforms (Arm® SoC Designer, System C, etc.), or emulation. The incredibly fast PowerBaum model provides the horse power for users to run real world scenarios and even software routines to analyze and characterize the power consumption of their designs. Now designers and architects no longer have to compromise by pruning down the workload and design to meet the limited capacity of other power analysis solutions in the market. Instead, they can analyze the whole design with realistic scenarios. See how PowerBaum is used in a typical power analysis flow.
Power models generated by PowerBaum provide users with very fast and accurate power analysis including average power and dynamic power as well as switching and leakage power.
PowerWurzel
PowerWurzel is Baum’s gate-level simulation engine used for training PowerBaum power models. Combining PowerWurzel with PowerBaum creates a powerful and efficient flow to generate extremely fast and accurate power models.
See how PowerWurzel fits into the power analysis flow.
PowerSpion
PowerSpion is a fast and light tool that customers can adopt in their everyday RTL development cycle to closely monitor various power metrics, such as
- Clock gating ratio (CGR)
- Clock gating efficiency (CGE)
- Clock gating enable efficiency (CGEE)
- Operational clock gating ratio (OCGR)
PowerSpion requires only RTL design and FSDB generated from RTL simulation to predict clock gating metrics. It also offers a linting feature to check if there is any redundant or misused ICGs in your RTL.
Tool Flow
The flow for generating and using power models from PowerBaum occurs in two parts: 1) The power modeling phase and 2) The power analysis phase.
Power Modeling Phase
PowerBaum is used in the power modeling phase to compile the power model and to train it with a short set of gate-level power vectors. Using these vectors, a gate-level power estimation tool, such as PowerWurzel, is used to train the model with gate-level accuracy. Once the training is complete, the power model is ready for use in RTL or ESL simulation (power analysis phase). PowerBaum can also accept RTL FSDB/VCD and internally generate gate-level power vectors. This is a convenient option when gate-level vectors are not ready in the early stage of the design.
The power modeling phase is a one-time process to create the power model and, once created, the power model can be used in multiple simulation environments (portable) and with many different scenarios.
Power Analysis Phase
After the power model is created by PowerBaum, it easily integrates into various simulation environments (RTL simulation, ESL simulation, and emulation) for very fast and accurate power analysis. Users can run the power models with multiple different realistic scenarios or even under real software loads. With PowerBaum’s power models, users can analyze both dynamic and average power to identify and isolate power issues in the design and fix them.
Features
- Design hierarchy support (power models at any level of the hierarchy)
- Parallel power modelling
- Power analysis with multiple power models
- Baum emulator PM: power model as hardware
- Separate reports for IO pad/memory/macro cells
- Power optimization guidelines
- Support for multi-clock, multi-VDD and dynamic frequency scaling
- Power analysis across temperature variations
- DC (don’t care) blocks
- Power analysis using FSDB/VCD
RTL Optimization
Early power-related design decisions have the most potential to minimize power consumption in a semiconductor design. Integration of PowerBaum into simulation environment is a great fit for RTL optimization. Therefore, RTL designers working on a variety of semiconductor designs, from data centers and CPUs to automotive ICs, can use PowerBaum to quickly analyze and minimize power consumption in the early design phase to manage power most effectively. PowerBaum’s power analysis speed is tens of times faster than current competitors.
AI Chip Design
AI processors, which are developing rapidly in recent years, are composed of numerous processing elements (PEs). For this reason, the AI chip has a very large size and there are many signals to be processed, so the demand for power analysis is high. However, current competitors that can analyze power only for the entire design require a lot of time and resources. PowerBaum provides AI chip designers with power analysis results with high speed and high accuracy. After the power model is created for only one PE block, power analysis can be performed on the PE array.
Power Debugging
In semiconductor design, the key to debugging the power issues is dynamic power analysis (analyzing the power waveform). Therefore, PowerBaum’s ability to run dynamic power waveform analysis for different scenarios swiftly makes it a best-in-class power debugging platform for semiconductor design. The figure on the right illustrates critical power issues in a GPU design during the idle state. The Designer was able to lower average power consumption by 22.7% with dynamic power analysis. By analyzing only average power or window of high activity, designer would not have found the problem.
Emulator Support
Performing the accurate power analysis of switching activity from the real software workloads is not possible using simulation software. Hardware emulation provides the speed and flexibility to analyze power under real operating conditions of the design. In PowerBaum, a combination of accurate Baum power models with hardware emulation creates an ideal solution for identifying and analyzing power problems in the design of large systems. Users have seen over 1,000 times speed-up compared to competing power analysis solutions when PowerBaum is used together with hardware emulation.