Achieving energy efficiency in chip designs continues to be a critical need in system on chip (SoC) designs. For example, battery lifetime was rated as the number one dissatisfaction factor with mobile phone users as surveyed by JD powers. Yet, with the slowdown of Moore’s Law, engineers are faced with adding power-consuming complexity to their designs to achieve their performance goals, making energy efficiency even more critical.
The three fundamental constraints for architecting a SoC are power, performance and area (PPA). Area can be easily estimated and performance can be analyzed through virtual platforms, abstract modeling of hardware prototyping.
Power modeling and analysis remain the most underdeveloped solutions in the design of SoCs. The semiconductor industry relies on ad hoc tools with little or no automation, abstract power models without a path to implementation or late-stage tools targeting gate-level or later when change is difficult and costly. All are prohibitively slow.
Engineers need a power solution much earlier when there is more opportunity to optimize power and gain better energy efficiency of their chip designs.