PowerMesser Features
- Digital on-chip power meter for real-time silicon power monitoring and opitmization
- Automatically generated from your design using AI-driven modeling
- Low latency (~10 cycles)
- Low overhead (~7k gates regardless of design size)
- High accuracy (10~15% vs gate-level analysis)
How PowerMesser Works
PowerMesser is hardware implementation of Baum’s accurate and lightweight power model, which is automatically generated from your chip design using AI-powered power modeling technique. With a near-constant footprint (~7k gates) regardless of design size and high-accuracy (10~15% error vs gate-level analysis), it enables real-time monitoring and fine-grained power optimization of your chip.
Advantage of on-chip power meter:
- Real-time power monitoring and optimization
- Proactive power and thermal management
- Accurate and fine-grained power debugging in silicon with real workload
PowerMesser Integration Flow
PowerMesser can be integrated into your chip as 1) a netlist or as 2) a hardened IP.
PowerMesser Integration with Emulator
Deploy PowerMesser alongside your target design on the emulator and experience on-the-fly power analysis directly within hardware emulation—uncovering power bugs and peak power issues across complex SoC workloads.