Power modeling solutions with the highest level of accuracy and 100x faster power analysis performance
Overview
Baum is uniquely positioned in the market because our power modeling solutions maintain the highest level of accuracy customers demand while providing them with two orders of magnitude (100X) faster power analysis performance. This unique combination of accuracy and speed allows designers to run a variety of realistic simulation scenarios with a much larger piece of the system, which has not been possible with other solutions in the market.
Baum removes the compromising on the length of the simulation or the size of the design to be analyzed. Typically, with other solutions in the market, the designer is required to limit the amount of simulation time to a small window because the analysis speeds are very slow. Existing solutions also require the designer to prune down the analysis to a small block because they have limited capacity. With Baum, there is no need to make these compromises. The unique capabilities of Baum’s power models expand the realm of possibilities for a designer to analyze bigger and bigger designs and allowing them to run realistic scenarios and workloads on those designs.
In addition, Baum’s power models can be used much earlier in the design cycle (shifting left). Using Baum’s power models in ESL environments provides users the means to truly understand power and thermal constraints at the system level and understand power management in both the hardware and software domains. This allows architects and designers to make true power and performance trade-offs in a single simulation with congruent power and performance models.
Once Baum’s power models are created, they can be easily ported into any simulation environment including ESL simulation (Virtual Platforms), RTL simulation, and emulation. This portability enables reuse and consistency across platforms and allows 3rd party IP providers to offer power models of their IP to their end users.
Low Power Design
As the rate of Moore’s law is slowing down and becoming much more expensive to achieve, designers are pressured to pack more power consuming circuitry into their designs to achieve their performance goals. No longer can designers rely on jumping to a smaller process node to achieve higher performance and lower power every two years. Those days are limited.
These pressures are pushing designers to optimize the power of their designs more aggressively and to find new ways to harvest energy. They need new tools that allow them to optimize both average and dynamic power and to find and to isolate areas of their designs that are wasting energy.
It is well known that the largest power optimizing opportunities occur early in the design cycle, yet existing solutions in the market that maintain any form of accuracy only provide designers analysis capability late in the design cycle at a mature RTL phase or gate-Level phase. Designers need a tool that will allow them to “shift left” and analyze and optimize power earlier in the design cycle at the system level where the opportunities to optimize performance are the greatest.
Baum provides just such a solution with our power models. They are the fastest models in the industry that maintain implementation accuracy. Baum’s power models run orders of magnitude (100x) faster compared to competing technologies while maintaining gate-level power accuracy giving users the best of both words. These unique capabilities allow users to run system level simulation with realistic workloads to reduce and optimize the power consumption in their designs. With the dynamic power analysis capabilities of our power models, users can easily zero in on the exact parts of the design that are consuming excess power and fix it.
Software/Hardware Power Profiling
System architectures of today’s designs employ much more hardware and software interaction than in the past. Software power management plays a key role in managing the power and thermal characteristics of a system. In addition, the activity levels of software running on a device play a key role in the overall power consumption.
Yet existing solutions in the market today don’t provide designers a means to analyze power accurately with realistic software scenarios. This prevents them from truly understanding if their power management routines are doing their job correctly or to understand the power and thermal effects of software activity on their designs.
Baum’s power models provide both the speed and accuracy to run realistic software loads on the entire design enabling designers to understand the hardware/software interaction as it relates to power consumption and thermal efficiency. In addition, Baum’s power models integrate into ESL simulation environments allowing designers to easily run their software and analyze and optimize power. The following data sheet provides more information pertaining to Baum’s power model’s integration into ESL virtual platforms [link to PowerBaum Brochure – need to provide name and email to access].
Power and Performance Tradeoffs
Power, performance, and area are the three axis of design architecture. Trading off and optimizing each are key to a product’s success and marketability. Techniques for optimizing area are relatively straightforward and well understood. Optimizing performance is typically done early in the design cycle at the architectural or micro-architectural level. Optimizing power has always been difficult; there is really no methodology that allows architects and designers to accurately optimize power while they are making performance trade-offs. Existing power analysis solutions are either too slow, applied too late in the design cycle, are not accurate, or cannot be automated. Their limited capabilities are huge barriers to easily and accurately provide a power/performance methodology allowing designers and architects to understand and optimize the trade-offs between the two.
Baum’s power models are the answer. They maintain the required implementation accuracy for power analysis to be congruent with the performance analysis while, at the same time, accelerate power analysis speeds by orders of magnitude (100X) compared to existing solutions. Now architects and designers can make true power performance tradeoffs running realistic scenarios, under realistic software loads. They can make changes in the design to increase performance and immediately understand the effects of the changes on power consumption. For more information, click on the following link to see how Baum’s power models integrate into ESL environments for understanding power and performance trade-offs [link to PowerBaum Brochure – need to provide name and email to access].
IP Power Modeling
IP companies have always struggled creating and delivering accurate power models to their customers, who desperately need them to validate and optimize their SoCs. This is because there has been no way to automatically create accurate models for IPs in a secure and portable manner. Lack of validated models from IP vendors have led designers to rely on various ad hoc methods to analyze and optimize the power of their designs. This has created a huge gap in their methodology and added undo risk to their projects.
Baum answers this need by providing a methodology for IP providers to automatically create power models for their IPs. These models are very fast and accurate (implementation accurate) and, most importantly to IP providers, they are very portable and secure. IP providers can rely on Baum solutions to quickly create power models of their IPs through an automated flow and deliver these models securely to their customers. The IP power models are portable and can be used in any simulation environment (RTL simulation, ESL/Virtual Platform simulation, or emulation).
Using Baum power models for 3rd party IP closes the methodology gap in analyzing and optimizing power for the end user and creates confidence with the designers that the 3rd party IP is meeting its power budgets.
Power Sign-off
Power sign-off prior to tape out has been a near impossibility with existing solutions in the market. Because existing power analysis solutions are much too slow to run realistic scenarios, designers struggled to prove their designs will meet the power budget under a real load. Running a very small slice of a scenario with just a piece of the design does not validate power for sign-off but, unfortunately, this is only what existing solutions are capable of.
Baum power models combine the speed and accuracy required to break through these barriers for power sign-off. They run 100x faster than existing solutions allowing designers to run realistic scenarios (real loads) with very high accuracy. In addition, Baum’s technology has a much higher capacity than existing solutions in the market allowing users to analyze the power for their whole design. Now users can use Baum’s power models in power sign-off before tape-out and have confidence that their design will meet its power budget.
Discover Security Vulnerabilities
The cryptography used in security chips is vulnerable to side channel attacks in which the attacker studies the power consumption of the device, such as with a smart card. The attack can non-invasively detect cryptographic keys and other secret information from the circuit. These attacks enable an adversary to compute the secret encryption keys used to protect the information.
What if designers could uncover these security vulnerabilities and fix them before the design of the device was finalized? With Baum’s power models, this is now possible. Baum power models provide the speed necessary to run scenarios required to analyze the power output of the device which reveal vulnerabilities. Other solutions have no way to achieve this because they lack the speed or accuracy necessary to run the real workload that expose these side channel attacks.
IR Drop Analysis
Ensuring the integrity of the power distribution network of a device is one of the key components in design closure. As process dimensions shrink with faster switching frequencies they induce much higher switching currents in the power networks. In addition, shrinking device dimensions cause higher resistance in the networks and interconnects. This increase in current and resistance makes todays devices much more vulnerable to IR drop in the power grid causing the device to run slower, increasing noise, and reducing operating margins. Increasing noise in the device can often lead to device failures. A robust power distribution network is key to reliable operation of the device in high-performance designs.
IR drop analysis is key to ensuring the reliable operation of the chip. IR drop analysis tools in the market rely on the designer to understand and apply peak power scenarios for the analysis input. Peak power is either estimated or modeled from very short simulations and so risk missing real peak power behavior. Designers need the capability to run real loads on the device to really understand the peak power conditions. Unfortunately, existing tools in the market are too slow to run realistic loads on the device. That was certainly true until Baum came along.
Now with Baum power models, designers can understand peak power constraints from realistic scenarios and workloads. These peak power parameters can then be fed back as inputs to the IR power analysis tools for a better and more realistic IR drop understanding resulting in a more robust and reliable power grid design.