Home > PowerMesser
PowerMesser is an AI-powered digital on-chip power meter designed for real-time silicon power monitoring and optimization, offering low latency and minimal overhead.
PowerMesser Features
- Digital on-chip power meter for real-time silicon power monitoring and opitmization
- Automatically generated from your design using AI-driven modeling
- Low-latency (~10 cycles), low-overhead (<20k gates regardless of design size), high accuracy (10~15% vs gate-level analysis)
How PowerMesser Works
PowerMesser is hardware implementation of Baum’s accurate and lightweight power mode, which is automatically generated from your design using AI-powered power modeling technique, tailored for each chip design. With a near-constant footprint (<20K gates) regardless of design size and high-accuracy (10~15% error vs gate-level analysis), it enables real-time monitoring and fine-grained power optimization of your chip.
Advantage of on-chip power meter:
- Real-time power monitoring and optimization
- Proactive power and thermal management
- Accurate and fine-grained power debugging in silicon with real workload
PowerMesser Integration Flow
Once PowerMesser is synthesized from your design netlist, it can be integrated into your chip as 1) a netlist or as 2) a hardened IP.
