Design Flow


PowerBaum Flow Description


PowerBaum automatically generates fast yet very accurate power models, which plug easily into a variety of 3rd party EDA tools such as RTL simulators, ESL simulators, or gate-level power analysis tools. It enables system-level power analysis for an entire SoC with realistic scenarios, which is impossible with other currently available technologies today.

PowerBaum takes RTL (Verilog) designs, a cell library, gate-level netlists (Verilog), and switching information (FSDB or VCD) along with a reference gate-level power simulation result. It automatically generates a high-level power model of the given design in our proprietary binary format. The power model is then linked with a commercial RTL or ESL simulator (e.g., Synopsys VCS and Platform Architect). While the RTL or ESL simulator runs, it generates power waveforms on the fly.

 

Flow Diagram